Fixed ASIC designs limit the rate of deployment of new features on electronic devices and the hardware changes to support new features are expensive in term of both cost and time. As a result, designs of programmable electronic devices which allow users to deploy new features by means of software have been becoming increasingly attractive. Consequently, both wireline and wireless network systems are moving forward the software-defined architectures, namely software-defined networks and software-define radios. Each electronic device in these network systems includes one or several programmable engines, wherein each of the programmable engines is equipped with a plurality of configurable memories/registers which are reprogrammable by the users so that the device can adapt to and support new features. All of the configurable registers in the programmable engine are controlled (e.g., read or written) by the users and their contents are used by the functional circuits of the engine. Any change in the contents of those configurable registers will change the features of the engine.
In some designs, the plurality of configurable registers in the programmable engine can be configured with one or more configuration controllers. Specifically, each of the configuration controllers directly connects a plurality of configurable registers, wherein each configurable register has a unique register address that allows the user to write to and read from the targeted configurable register. During its operation, each of the configuration controllers receives a write or read request along with the requested address from the user. Upon receiving the write or read request, the configuration controller identifies the register in its plurality of configurable registers to write to or read from and performs a write to or read operation from that identified configurable register. The configuration controller then reports the results of the write to or read operation back to the user after the operation is done.
Assuming there are N configurable registers controlled by a configuration controller in the programmable engine, wherein each of the configurable registers is n-bit wide in size, then there are 2×N×n connecting wires between this configuration controller and these N configurable registers for both write and read data signals. For large N and n, the number of connecting wires required to configure these configurable registers becomes very large, which creates hard physical wiring congestion at the configuration controller, causing significantly increases in both timing violation and silicon area of the programmable engine utilizing these configurable registers.
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent upon a reading of the specification and a study of the drawings.